Chapter 13 - Technology Mapping

Abstract

This chapter discusses technology-mapping algorithms for field-programmable gate arrays (FPGAs). It emphasizes state-of-the-art algorithms that have been, or most likely will be, reduced to practice. It discusses mapping algorithms for different objectives, such as area, timing, and power, as well as mapping algorithms that take advantage of heterogeneous resources in modern FPGA devices. Technology mapping is an essential step in an FPGA design flow. It is the process of converting a network of technology independent logic gates into a network comprising logic cells on the target FPGA device. Technology mapping has a significant impact on the quality of the final FPGA implementation. FPGA technology mapping has been and continues to be a subject of active research. A general trend is to integrate technology mapping with other steps in the FPGA design flow to improve the quality of final implementations. As semiconductor technologies advance, new FPGA architecture features are being introduced to improve area utilization, performance, and power consumption. For example, architectures have been introduced or proposed that use large lookup tables (LUTs) (much larger than traditional 4-/5-LUTs) or multiple supply voltages. New mapping techniques are being developed to take advantage of these architecture features.