Abstract

Ultimately, devices are interconnected into complex circuits—logic, memory, and routing—to provide the functionality expected from various processors (ASIC, microcontroller, GPU, CPU, etc.) or systems on chip (SoC). For future processors, the use of advanced CMOS technologies in sub-10nm nodes requires high-performance MOSFETs working at low power consumption. In addition, the demand for integrating multiple functionalities in SoCs is also growing, for example, for wireless communication. To meet such requirements, innovation is necessary to integrate new semiconductors as channel materials. The so-called high-mobility semiconductors such as Ge, SiGe, and III-V compound semiconductors are the leading candidates to obtain the required functionality yet providing benefits in power and performance. To provide a robust and manufacturable technology, one needs to cointegrate such materials on the same technological platform. Various challenges must be overcome for achieving such a hybrid CMOS technology, from material integration aspects to device fabrication and design-technology cooptimization.

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