Abstract

Chaotic sequences are good candidates to replace random sequences in many digital electronic applications, this is due to their stochastic appearance and, under certain considerations, easy hardware implementation. On the other hand, Compressed Sensing (CS) technique allows the efficient acquisition and reconstruction of signals from a smaller number of samples than that required by Shannon-Nyquist sampling theorem. A critical point in this technique is the choice of sampling implementation, usually random sequences are used. These sequences are computationally expensive to generate, so in this work the use of chaotic sequences is studied. This paper validates by the design and hardware implementation in a PSoC (Programmable System-on-Chip), Zedboard FPGA (Field-Programmable Gate Array) a signal acquisition system employing chaotic Compressed Sensing. Performance quantifiers of the implemented system are proposed and the results obtained are reported, which show that the chaotic systems present a behavior comparable to the classic ones.

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