Chaotic Clock Driven Cryptographic Chip: Towards a DPA Resistant AES Processor

Abstract

Designing a tamper-resistant microchip for small embedded systems is one of the urgent demands of the computing community nowadays due to the immense security challenges arising particularly in massively connected networks. One of the major threats to secure smart card chips is the ability of Side Channel Attacks (SCA), such as Correlation Power Analysis (CPA) and Correlation Instantaneous Frequency Analysis (CIFA) to increase the vulnerability of the secured cipher text to attacks even when the state of the art Advanced Encryption Standard (AES) is used. In this paper we explore the possibility of using chaotic clocking to protect AES chips against CPA and CIFA attacks. Our findings reveal that chaotic clocks, although not random, can effectively provide this protection with a low power envelope. Chaotic clocks derived from two different chaotic systems were used for testing in order to confirm the findings. Two FPGA boards running AES were driven using these chaotic clocks in order to prove the applicability of the proposed security enhancement technique.