Abstract
The gate-all-around (GAA) nanosheet (NS) junctionless transistor (JLT) is an attractive candidate for advanced technology nodes in CMOS scaling. Here, the channel width-dependent transconductance (gm) degradation and threshold voltage (Vth) shift of GAA NS JLTs were investigated via numerical simulation. Compared to bulk neutral channels, a pronounced surface accumulation channel limited the overall electrical characteristics of GAA NS JLTs at narrow widths. Additionally, the variation in Vth of GAA NS JLTs was much smaller than that in tri-gate JLTs. Quantum mechanical effects in GAA NS JLTs with a very narrow width were also investigated.
Highlights
Junctionless transistors (JLTs) are one of the most promising candidates for minimizing unwanted short-channel effects in aggressively scaled devices for advanced technology nodes.1,2 The unique device structures without PN junctions of junctionless transistor (JLT) enabled a very simple fabrication process, and bulk conduction in JLTs leads to less mobility degradation, improved low-frequency noise, and better reliability against operating bias stress.1–6 An additional implantation process in source and drain (S/D) regions can solve the issue regarding the S/D series resistance in JLTs.7 Threshold voltage (Vth), flatband voltage (Vfb), Si thickness, and transconductance are the most important electrical parameters for understanding the operation of JLTs
The channel doping concentration (Nd), thickness of the gate-dielectric, and device Si thickness of the GAA NS JLTs were set to Nd = 1019/cm3 for JLTs and Nd = 1014/cm3 for conventional IM transistors, tox = 1.2 nm, and tsi = 10 nm, respectively
The defined value of the low-field mobility (μ0) was 150 cm2/Vs for JLTs and 500 cm2/Vs for IM transistors, and the drain current was simulated by using a universal relationship between the electric-field (E-field) influenced mobility and the transverse E-field from the gate,13,18 μ f ield
Summary
Junctionless transistors (JLTs) are one of the most promising candidates for minimizing unwanted short-channel effects in aggressively scaled devices for advanced technology nodes. The unique device structures without PN junctions of JLTs enabled a very simple fabrication process, and bulk conduction in JLTs leads to less mobility degradation, improved low-frequency noise, and better reliability against operating bias stress. An additional implantation process in source and drain (S/D) regions can solve the issue regarding the S/D series resistance in JLTs. Threshold voltage (Vth), flatband voltage (Vfb), Si thickness, and transconductance (gm) are the most important electrical parameters for understanding the operation of JLTs. Threshold voltage (Vth), flatband voltage (Vfb), Si thickness, and transconductance (gm) are the most important electrical parameters for understanding the operation of JLTs. Field-effect transistors (FETs) with gateall-around (GAA) nanosheet (NS) structures [or so-called stacked nanowires (NWs)] have been extensively considered as attractive devices to overcome fundamental limits in conventional CMOS scaling.. GAA nanowire (NW) JLTs have shown significant bias-temperatureinstability (BTI) improvement, better subthreshold swing (SS), and lower 1/f noise results, as compared to conventional GAA NW transistors.. Numerical simulations were used to investigate channel width-dependent electrical characteristics of GAA NS JLTs, transconductance degradation and threshold voltage shift, and to compare these with those of conventional inversion-mode (IM) transistors with the same channel shapes. This work provides important information for better understanding operation of the GAA NS JLTs for further continuation of CMOS scaling down
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