Abstract
In this work, the channel design space for scaled strained Ge (s-Ge) buried channel (BC) MOSFETs is examined by simulations and experiments. The identified Ge channel layer structure is scalable to sub-30nm devices. Furthermore, strained Ge buried-channel MOSFETs with an ultra thin (1.5nm) Si cap are demonstrated with a 6/spl times/ hole mobility enhancement over the Si universal hole mobility. Compared with surface channel Ge MOSFETs. buried strained Ge channel structures can be integrated with fewer processing challenges to achieve a significantly enhanced hole mobility and an improved electron mobility.
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