Abstract

Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Channel Charge Injection (CCI) effect is one of major non-ideal parameters existing in TG switches corrupting modulator total SNDR, its linearity and its total gain. In this paper, a comprehensive analysis of CCI non-ideal effect on CMOS transmission gates (TGs) and SC integrator using actual clock timing and charge injection model will be presented. The relation between output error and input signal level will be extracted and finally its modeling for switched capacitor integrator using probabilistic equations in z-domain will be presented. Evaluation and validation for extracted models were performed via behavioral and transistor-level simulations for an implemented third-order modulator using 0.18um CMOS technology in SIMULINK and Agilent ADS environments.

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