Chamber distortion control in a high volume manufacturing foundry environment

Abstract

As chip makers move to advanced nodes and device geometries shrink, design and production costs have risen rapidly. As a result, it has become increasingly critical to reduce costs in established technology nodes by increasing device yield. For a given process, differences in individual process chambers can lead to process variations that may have a large impact on both overlay control and yield management. Chamber distortion control represents an effective way to detect wafer- and lot-level process variation and excursions by monitoring the process-induced in-plane displacement contribution to overlay. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density, full-wafer distortion data set with throughput suitable for a high volume manufacturing (HVM) environment. This paper represents a collaborative effort between United Microelectronics Corp. (UMC) and Ultratech Inc. to evaluate the application of this technology in an HVM logic foundry. Currently, furnace-based thermal processes are key steps that cause out of control wafer distortion if the process variation is not monitored. This paper demonstrates that CGS technology can successfully identify chamber displacement variability and that statistical process control (SPC) using factory automation (FA) fully automates the detection of such excursions for use in an HVM environment.