Challenges of advanced wafer level packaging technology: Cost-effectiveness, integration and scalability

Abstract

Currently various wafer level packaging (WLP) technologies are now cruising at a very high altitude, especially in mobile and portable applications. This is significant trend in packaging business: over 25 billion WLP units are expected to be mounted in smart-phones, tablet PCs or portable devices in 2012. Cost reduction together with miniaturization remains the main driver for adoption of WLP technology. Compared to conventional wire bonding and flipchip packaging, wafer level packaging needs higher capex investment because it has fab-like tools for redistribution process with thin film metals and dielectric polymers. Further cost reduction is a critical factor for penetration into market beyond current market boundaries. And WLP size is increasing with higher IO density and integration of functionality, so board level reliability would be key challenge for moving into broader application areas. In this paper, there will be discussion of technical challenges and market needs of advanced wafer level packaging technology, including fan-in, fan-out (FO), bumping and TSV (Silicon Through Via) etc. And potential solutions and industry approach for those challenges will be presented. Some deeper insights on business opportunities and cost reduction approaches in wafer level packaging in materials and processes will be presented. Lastly new trend of wafer level packaging technology will be discussed including large panel or scalability for high volume production.