Challenges of 29nm half-pitch NAND Flash STI patterning with 193nm dry lithography and self-aligned double patterning

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High NA (1.35) Immersion litho runs into the fundamental limit of printing at 40-45nm half pitch (HP). The next generation EUVL tool is known to be ready not until year 2012. Double patterning (DP) technology has been identified as the extension of optical photolithography technologies to 3xnm and 2xnm half-pitch for the low k1 regime to fill in the gap between Immersion lithography and EUVL. Self Aligned Double Patterning (SADP) Technology utilized mature process technology to reduce risk and faster time to market to support the continuation of Moore's Law of Scaling to reduce the cost/function. SADP uses spacer to do the pitch splitting bypass the conventional double patterning (e.g. Litho-Freeze-Litho-Etch (LFLE), or Litho-Etch-Litho-Etch (LELE)) overlay problem. Having a tight overlay performance is extremely critical for NAND Flash manufacturers to achieve a fast yield ramp in production. This paper describes the challenges and accomplishment of a Line-By-Spacer (LBS) SADP scheme to pattern the 29nm half-pitch NAND Flash STI application. A 193nm Dry lithography was chosen to pattern on top of the amorphous carbon (a-C) film stack. The resist pattern will be transferred on the top a-C core layer follow by spacer deposition and etch to achieve the pitch splitting. Then the spacer will be used to transfer to the bottom a-C universal hardmask. This high selectivity a-C hardmask will be used to transfer the 29nm half-pitch pattern to the STI. Good within wafer CD uniformity (CDU) 10) case through the whole SADP process. Finally, cost analysis for 193nm dry lithography SADP will be compared to 193nm Immersion lithography SADP.