CG-in-PG architecture implementation for power reduction in FSMs

Abstract

By gating the power supply of the inactive part of the finite state machine (FSM) circuit, total power is reduced but the active part continues to dissipate power. So, there is a possibility of applying clock gating (CG) to the active part of the power-gated FSM. A transition may happen in which the states do not change but output changes. This issue has not been addressed by the conventional CG, so, for reducing the switching of register during CG and to overcome the issue, conventional CG has been modified by splitting the input latch of the FSM circuit. The architecture termed as CG-in-PG is designed in such a way that when one sub-FSM is inactive it adopts power gating (PG) for power reduction and other sub-FSM seeks for possible CG during its active period. So, both the sub-FSM is capable of reducing power either by PG or by CG depending on whether it is in inactive mode or active mode. To the best of our knowledge, this is the first ever approach of applying CG after power-aware genetic algorithm (GA)-based bi-partitioning and encoding of FSM for power-gated design. The synthesis of the proposed design has been implemented in Cadence digital synthesis tool. The results show 36.94% average saving after applying CG-in-PG with respect to only PG.