Cellular Neural Network (CENN) FPGA implementation using multi-level optimization

Abstract

Cellular Neural Network (CeNN) has been widely adopted in image processing tasks, which is considered as a powerful paradigm for embedded devices. Recently, digital implementations of CeNNs on FPGA have attracted researchers from both academia and industry due to its high flexibility and short time-to-market. However, most existing implementations are not well optimized to fully utilize the advantages of FPGA platform with unnecessary design and computational redundancy that prevents speedup. We propose a multi-level optimization framework for energy efficient CeNN implementations on FPGAs. In particular, the optimization framework is featured with three level optimizations: system-, module-, and design-space-level, with focus on computational redundancy and attainable performance, respectively. Experimental results show that our framework can achieve an energy efficiency improvement of 3.54× and up to 3.88× speedup compared with existing implementations.