Cell‐Based ASIC Design Methodology

Abstract

This chapter contains sections titled: What are the major tasks and personnel required in a chip design project? What are the major steps in ASIC chip construction? What is the ASIC design flow? What are the two major aspects of ASIC design flow? What are the characteristics of good design flow? What is the role of market research in an ASIC project? What is the optimal solution of an ASIC project? What is system-level study of a project? What are the approaches for verifying design at the system level? What is register-transfer-level (RTL) system-level description? What are methods of verifying design at the register-transfer-level? What is a test bench? What is code coverage? What is functional coverage? What is bug rate convergence? What is design planning? What are hard macro and soft macro? What is hardware description language (HDL)? What is register-transfer-level (RTL) description of hardware? What is standard cell? What are the differences among standard cell, gate-array, and sea-of-gate approaches? What is an ASIC library? What is logic synthesis? What are the optimization targets of logic synthesis? What is schematic or netlist? What is the gate count of a design? What is the purpose of test insertion during logic synthesis? What is the most commonly used model in VLSI circuit testing? What are controllability and observability in a digital c ircuit? What is a testable circuit? What is the aim of scan insertion? What is fault coverage? What is defect part per million (DPPM)? Why is design for testability important for a product's financial success? What is chip power usage analysis? What are the major components of CMOS power consumption? What is power optimization? What is VLSI physical design? What are the problems that make VLSI physical design so challenging? What is floorplanning? What is the placement process? What is the routing process? What is a power network? What is clock distribution? What are the key requirements for constructing a clock tree? What is the difference between time skew and length skew in a clock tree? What is scan chain? What is scan chain reordering? What is parasitic extraction? What is delay calculation? What is back annotation? What kind of signal integrity problems do place and route tools handle? What is cross-talk delay? What is cross-talk noise? What is IR drop? What are the major netlist formats for design representation? What is gate-level logic verification before tapeout? What is equivalence check? What is timing verification? What is design constraint? What is static timing analysis (STA)? What is simulation approach on timing verification? What is the logical-effort-based timing closure approach? What is physical verification? What are design rule check (DRC), design verification (DV), and geometry verification (GV)? ...