Cell-aware test generation time reduction by using switch-level ATPG

Abstract

In this paper, we propose an efficient test flow for Cell-Aware Test (CAT) to drastically reduce the time for CAT-enhanced test generation at the cell level. In CAT, the detail transistor-level circuit simulation is used to find appropriate test patterns and it has been considered as very time consuming. To solve this problem, first, we exploit Switch-Level ATPG (SL-ATPG) and experimentally show that it can efficiently generate test patterns in the CAT flow. Second, based on layout-oriented defect generation method, we propose an algorithm to automatically inject those defects into the switching network used in SL-ATPG, for cells in the library. Third, note that the traditional ATPG is primarily based on the stuck-at-fault and transition-fault models, it is difficult to find small-delay faults. However, the same defects are likely to be detected by observing the short-circuit current, so we propose current-based checks for a pattern generation method which are able to detect the existence of a short-circuit path. Finally, we compare the simulation time of detailed circuit simulation and of SL-ATPG in CAT. The experiment is based on a commercial 180nm CMOS standard cell library. Moreover, it shows that SL-ATPG method can successfully reduce the simulation time by about 403X.