Cell devices for high-density flash memory

Abstract

By utilizing the fringing electric field from the control gate of cells in NAND flash memory string, the source/drain in the cells could be removed, which improves cell scalability and gives very positive effects. In this scheme, cells with underlapped S/D or localized buried oxide in the space shown more reasonable read current characteristics. For NOR flash memory, cells with recess channel structure have studied. We demonstrated successful operation of 4-bit/cell using the recess structure and found no interference in a cell and adjacent cells. Finally, we compared measured RTN in FinFET SONOS and saddle SONOS devices. The current fluctuation of the FinFET devices is higher by ~3 times than that in the saddle devices. We expect that our approach is very promising for future high density and high performance flash memory technology.