Cell design methodology for balanced carry-carrybar circuits in hybrid-CMOS logic style

Abstract

In this paper, a novel systematic design methodology in the category of hybrid-CMOS Logic style is proposed and used for designing full swing balanced Carry-Carrybar circuits. The critical path of the presented designs consists of only one pass-transistor, which causes low propagation delay. High driving capability, full-balanced full-swing outputs and low number of transistors of basic structure of the designs are the obvious features of them. As known, Hybrid-CMOS full adders can be divided into three modules. Four new full adder circuits with high performance and high drivability have proposed in this paper by embedding the circuits in carry module. Simulations have been performed with TSMC 0.13-μm technology using HSpice and show that the proposed circuits exhibit better performance in compare with previously suggested circuits. These circuits outperform their counterparts showing 52%-81% improvement in the power-delay product.