Abstract
Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.
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