Abstract

The first integration of a 256*256 buried-channel frame-transfer CCD (charge coupled device) image sensor with CCD-based reformatting circuitry to allow on-chip difference encoding for hierarchical lossless image compression is reported. The 28 frames per second pyramidal pixel output is in 3*3 pixel blocks with the center pixel first. The reformatting circuitry occupies 2% of the active chip area with an estimated power dissipation of 150 mu W at a 30-Hz frame rate. >

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