Abstract
The preliminary results of a development program to minimize beam perturbation resulting from ripple current generated by the CBA Main Magnet Power Supply are presented. The assessment of the magnitude and causes of the ripple generated led to a modification of the SCR Gate Driver and the addition of a bandpass amplifier correction loop which gave significant improvement. A description of the changes made and the results obtained are included. A second design approach was developed in which the timing of the SCR gate pulses is directly determined by a VCO. The results reported with this VCO Loop indicate superior performance particularly at frequencies below 60 Hz. A shunt transistor regulator design is proposed to minimize higher SCR switching frequency harmonics.
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