Cathodoluminescence and TEM characterization of defects in III-V materials grown on Ge-terminated Si substrates

Abstract

The growth of III-V materials on Si has been a major focus in electronic materials research for nearly a decade. The highly complementary properties of this heteroepitaxial system include high mobility and direct band gap in III-V materials and high crystalline quality, low cost and well-established technology of Si. However, the attainment of high crystalline quality III-V materials on Si suitable for minority carrier devices has been inhibited primarily due to the large lattice mismatch (˜4%) and thermal expansion mismatch (factor of ˜3) as well as the problematic nucleation of an ordered semiconductor on an elemental semiconductor. The epitaxial layer can contain threading dislocations, microtwins, stacking faults, antiphase domain boundaries (APBs) and/or have a poor surface morphology. A buffer layer can be added to improve the III-V material quality by accommodating the lattice mismatch at one or more interfaces and/or to provide a more suitable surface for nucleation. We have used TEM in conjunction with scanning cathodoluminescence (CL) intensity mapping for complete and accurate assessment of crystalline quality and defect densities within a range of ˜ 5×102 cm-2 to > 108 cm-2.