Case Study of Interconnect Analysis for Standing Wave Oscillator Design

Abstract

As a result of continuous downscaling CMOS technology, on-chip interconnects play a critical role in high-speed circuit design. In this paper, a geometry based accurate interconnect circuit model is extracted for high-speed circuit design and analysis. This is demonstrated through a 10 GHz standing wave oscillator (SWO) for global clock distribution. The results show that the skew of the clock is well controlled (about 1ps) while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. Hence, for high-speed circuits, the interconnect parameters should be predictable according to its geometry in order to avoid design iterations and speed time-to-market. Meanwhile, robust circuit architectures should be adopted for tolerating the parameter variations of interconnects.