Cascaded Systolic Honey-comb like Structure for Series Sorting

Abstract

The series sorting techniques are mainly used in searching, finding out closest pair, element uniqueness and frequency distribution in a set of data elements for statistical analysis. Using normal techniques in software approach, it consumes on an average from N x log(N) to N2 clock cycles for sorting set of N data elements. Hence when the set of data elements N is large, the processing time in series sorting becomes quite large. This situation is comfortable for Commercial-Communication applications but not for Non-Communication Radar Electronic Warfare (EW), where required clock cycles for data processing is the main bottle-neck for it.Thus essentially for Radar EW signal processing applications, a simple technique using ‘Cascaded Systolic Honey-comb like Structure’ is proposed for ‘Complete Series Sorting’ of set of N data elements where only N clock cycles are required for series sorting but at the cost of N (N-1)/2 basic comparators, which are easily implementable in FPGA-based-design.