Abstract
In this paper, a serial/parallel cascaded H-bridge (CHB) multilevel inverter is presented. The topology has the advantage of reduced number of switching devices, DC-sources and gate driver circuits. Consequently, cost and complexity are greatly minimised, providing the same number of output voltage levels even more compared to conventional structures and other topologies given in some recent literatures in which authors have proposed new topologies with reduced circuit devices count (RDC). The main contribution of this work is the ability to choose a set of harmonic order to be eliminated; in other similar works, PWM technique is only capable to minimise total harmonic distortion (THD) without eliminating selected harmonic which require a complex output filter. The feasibility and effectiveness of the proposed topology is evaluated with intensive simulation study and experimentally tested on a prototype using a field-programmable gate array (FPGA) to implement N-R algorithm for inverter selective harmonic elimination (SHE) control.
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