Abstract
Carry-save multipliers require an adder at the last step to convert the carry-sum representation of the most significant half of the result into a non-redundant form. This paper presents n/spl times/n multiplication schemes where this conversion is performed with a circuit operating in parallel with the carry-save array. The most relevant feature of the proposed multipliers is that the full 2n-bit result is produced, unlike similar multiplication schemes presented in the literature.
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