Carry free, bit parallel approximate squarers with linear complexity and constant delay

Abstract

This paper presents two simple combinational logic design approaches for bit-parallel approximate squarers of unsigned numbers. The design approaches are suitable for squarers of any bit length, and are particularly well suited for implementation in LUT-based FPGAs. It is shown that the hardware requirements grow linearly with the input bit width, as opposed to recent work where the complexity grows quadratically. This is a consequence of the optimized function selection algorithm which limits the number of input variables to each bit function. It is also shown that the critical path delay is independent of the input bit width. The proposed sets of Boolean equations are very simple to use and lend themselves very well to a parameterized HDL description. For a 7-bit input squarer, the maximum relative error (MRE) and average relative error (ARE) are as low as 9.44% and 2.47%, respectively. For very wide input, the MRE and ARE asymptotically approach 11.3% and 4.5%.