CARRIER RECOVERY AND CLOCK RECOVERY FOR QPSK DEMODULATION

Abstract

This paper deals with the design and implementation aspects of high data rate digital demodulators. The Existing remote sensing satellites support data rates of several hundred mega bits per second. The future trend is towards giga bit rate transmission. This necessitates for demodulators of the ground receive system to process faster and handle the ever-rising data throughput more efficiently. Different Satellites use different modulation schemes with variable data rates. In order to cater to the Multi mission /Multisatellite data reception requirements of a ground station, it is necessary to have greater flexibility and programmability features embedded in the design of demodulators. The demodulation techniques for Binary / Quadrature Phase shift Keying (BPSK/ QPSK) are well established and understood when implemented with analog circuits. The BPSK/ QPSK can be demodulated by different techniques such as squaring loop, Costas loop and others in analog domain. The Costas loop technique is adopted for developing the digital demodulator because unlike in Square Loop technique, in this the carrier recovery and data demodulation can be done simultaneously with simple blocks level design. The high data rate digital demodulator performs IF amplification, filtering and analog to digital conversion of the received IF signal followed by a Digital demodulator. The basic design strategy includes a configurable data rate BPSK/ QPSK demodulation with COSTAS loop circuitry utilizing the flexibility of FPGA implementation. The basic design considering a sampling clock from local clock oscillator operating at 125 MHz and 70 MHz carrier down converted to 30 MHz for 8 Mbps data rate (For BPSK). Later the sampling clock is increased to 250 MHz and the carrier is direct 70 MHz with data rate 42.4456 Mbps (For QPSK). The Performance of the Demodulator is evaluated using MATLAB simulation tools. The development has done with ISE implementation tools. The purpose of this paper is to evaluate the new technology by implementing a BPSK/QPSK demodulator on an ADC-FPGA board. A mathematical algorithm was developed and implemented with ISE tools for digital demodulator design. The input test signals from Modulation Simulators and signal generators have been interfaced to the FPGA board through Analog-To-Digital Converter (ADC). The recovered carrier output and I, Q demodulated data patterns have been verified through ISE tools and Wave Vision Software for FFT analysis.