Carrier mobility degradation due to high dose implantation in ultrathin unstrained and strained silicon-on-insulator films

Abstract

Based on electrical measurements and transmission electron microscopy (TEM) imaging, we propose an explanation for the electron and hole mobility degradation with gate length reduction in metal–oxide–semiconductor field effect transistors (MOSFETs). We demonstrate that ion implantation, normally used for source/drain doping, is responsible for transport degradation for short-channel devices. Implantation impact on electrons and holes mobility was investigated both on silicon-on-insulator (SOI) and tensile strained silicon-on-insulator (sSOI) substrates. Wafers with ultrathin Si films (from 8 to 35 nm) were Ge implanted at 3 keV and various concentrations (from 5×1014 to 2×1015 atoms cm−2), then annealed at 600 °C for 1 h. Secondary ion mass spectrometry enabled us to quantify the Ge-implanted atoms concentrations. The end-of-range defects impact on mobility was investigated with the pseudo-MOSFET technique. Measurements showed a mobility decrease as the implantation dose increased. We demonstrated that sSOI mobility is more sensitive to implantation than SOI mobility, without any implantation-induced strain relaxation in sSOI (checked using the ultraviolet Raman technique). A 36% (25%) holes (electrons) mobility degradation was measured for sSOI, while SOI presented a 21% mobility degradation for holes and 5% for electrons. Finally, the electrical results were compared with morphological studies. Plan-view TEM showed the presence of interstitial defects formed during ion implantation and annealing. The defect density was estimated to be two times higher in sSOI than in SOI, which is in full agreement with electrical results mentioned before. The results are relevant for the optimization of the source and drain regions of advanced nanoscale SOI and sSOI transistors.