Abstract
Carbon Nanotube FET (CNT-FET) is a promising candidate for the construction of future integrated circuits. However the presence of metallic tubes negatively affects delay, leakage power, and yield of such circuits. In this paper we compare four different CNT-FET configurations - shared tube, parallel tubes, transistor stacking, and tube stacking. In the presence of 10% metallic tubes, stacking configurations have potential to as much as double the yield for 4.1-4.4X delay penalty under iso-input capacitance and 3-7X lower leakage power compared to the non-stacked configurations. Analytical model and Monte Carlo simulation results for various logic gate sizes clearly indicate that an architecture that utilizes an appropriate combination of all four configurations is required to enable a better trade-off between delay, leakage power, and yield in the presence of metallic tubes.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.