Capture partial reluctance more efficiently for complex interconnect structure

Abstract

The partial reluctance based circuit analysis has been shown very efficient in capturing on-chip inductance effect because partial reluctance effect has much better locality than partial inductance. But efficient algorithms to extract sparse partial reluctance matrix for complex interconnect structure are needed. In this paper, the shielding effect of partial reluctance for general topology is illustrated and a 3-D extraction algorithm is developed to capture on-chip partial reluctance for multilayer complex interconnect structure. The partial reluctance estimation algorithm to estimate and truncate small mutual reluctance before extraction is developed to accelerate the partial reluctance extraction. The experimental results shows that our partial reluctance extraction approach is at least two orders of magnitude faster than inverting full partial inductance matrix but little accuracy is lost.