Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme

Abstract

As a special type of memory, Ternary Content Addressable Memory (TCAM) has been widely employed in network routers and various applications that require high speed table lookup. However, the large cell area and high static power consumption of traditional CMOS-based TCAMs have always constrained its advance toward higher capacity. Therefore, many non-volatile memory devices, such as ReRAM, FeFET, and MRAM, are emerging in TCAM designs to address these issues. However, SOT-MRAM devices with ultra-high write speed, low power consumption and small cell area are not effectively utilized in TCAM designs due to their low tunnel magnetoresistance (TMR) ratio, etc. In this work, first, combining the ultra-high performance of SOT-MRAM and the reliability of STT-MRAM, a 4T-3MTJ SOT/STT hybrid NV-TCAM structure with ultra-high integration density is proposed. However, to eliminate the lower match line utilization caused by the low TMR of SOT-MRAM, another highly reliable 7T-3MTJ NV-TCAM structure is proposed. Simulation results show that the proposed two TCAM structures can achieve search speed of 0.4ns and 0.15ns with only 4 and 7 transistors, respectively. While maintaining high performance, their write energy is only 0.133pJ/bit, a maximum reduction of 91.6% over existing TCAM designs. Meanwhile, the array-level simulations prove the great potential of the proposed design in terms of integration density and performance.