Capacitance–Voltage Technique Based on Time Varying Magnetic Field for VDMOSFET—Part I: Concept and Implementation

Abstract

In this article, we report a new capacitance–voltage technique ${C}$ ( ${V}$ ) to investigate the interface proprieties of MOS devices. This technique is based on surface potential modulation using time varying (ac) magnetic field. It is experimentally validated on vertical double diffusion MOSFET (VDMOSFET). Data show that the surface potential is modulated using external ac magnetic field. In fact, applying an ac magnetic field with dc voltage sweeping of VDMOSFET gate ( ${V}~_{G}$ ), we have been able, for the first time, to modulate the surface potential and measure the gate–source ( ${C} _{\text {GS}}$ ) and gate–drain ( ${C} _{\text {GD}}$ ) capacitances as a function of gate voltage ( ${V}~_{G}$ ) for P- and N-type transistors. Therefore, it offers a powerful tool to characterize different regions of the transistor and extract their technological and electrical parameters.