Capacitance Behavior With Voltage Bias in Phase-Change Memory for Fast Operation

Abstract

In this work, the time-delay effect on device operation caused by capacitance is studied in terms of phase-change memory (PCM) integrated with an ovonic threshold switch (OTS) selector. The capacitance studied in this work is the intrinsic capacitance associated with capacitive reactance of the PCM itself. The capacitance of the PCM in the amorphous state was measured, and it presents an exponential dependence on voltage bias. Through the simulation model of an OTS-PCM integrated device that considering the measured capacitance behavior, the time-delay characteristics of the integrated device for the SET process with various pulses were investigated. Results indicate that the onset of the threshold switching (TS) is delayed in the PCM but occurs early in the OTS with capacitance in the integrated device. In addition, it is found that the variable capacitance behavior can not only minimize the delay effect, but also accelerate the SET operation under certain conditions in the integrated device. Our results can provide practical guidance for the design of fast operating devices.