Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs

Abstract

A method is proposed for probabilistic testability analysis of digital circuits focusing on calculating the probabilistic controllability measures in terms of signal probabilities with the goal of assessment of pseudorandom test quality in digital circuits. The structure of the circuit is modeled as a macro-level network, where macros denote Fan-out-Free Regions (FFRs) of the circuit, which are represented as Structurally Synthesized BDDs (SSBDDs). SSBDD based representation allows signal probability calculation with higher speed and accuracy than using gate-level calculation approach. The proposed method is based on tracing true paths in SSBDDs, which avoids errors caused by signals' correlation and possible redundancy in the circuit, that is not possible in gate-by-gate probability calculation. A method is proposed for proving redundancy of faults, which is an extension of the same idea of SSBDD path tracing used for probability calculation. Experimental results show higher accuracy and considerable speed-up of probabilistic analysis using the proposed new macro-level approach, compared to gate-level calculation.