Abstract

The paper describes a hardware system carrying out point summation on elliptic curves. The implementation of basic function, which is modulo multiplication of huge integrals, is based on Krestenson’s basis. Such a summing unit has been used for hardware implementation of Pollard rho-algorithm. The paper also presents the performance of the mentioned unit.

Highlights

  • The need for keeping stored, processed and distributed data secret provoked a growing interest in cryptographic and identification techniques

  • Contemporary cryptography relies on elliptic curves over finite field GF(2m) and GF(p)

  • In order to increase the pace of VHDL (Very High Speed Integrated Circuits Hardware Description Language) code creation, which is the native code of the unit, a special function has been written in C++ language allowing an automatic unit code generation in VHDL device description language

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Summary

INTRODUCTION

The need for keeping stored, processed and distributed data secret provoked a growing interest in cryptographic and identification techniques. It has become convenient to use hardware FPGA units (Field Programmable Gate Array) for extremely fast operations carried out on elliptic curves GF(2m) according to the nature of the calculations. Information concerning this issue may be found in e.g. In order to accomplish our goal we have employed an unconventional approach: a technique relying on Rademacher’s-Krestenson’s basis allows multiplication operations to be converted into summing ones and taking advantage of previously generated tables Such operations are carried out by hardware systems and offer a substantial simplification of calculations

ELLIPTIC CURVES AND CORRESPONDING ARITHMETIC
POLLARD RHO PARALLEL METHOD OF FINDING DISCRETE LOGARITHM
THEORETICAL BASIS FOR IMPLEMENTATION OF FPGA SYSTEM
FPGA UNIT ARCHITECTURE
RESULTS
CONCLUSION
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