Abstract
The periodic behaviour of undithered Multi-stAge noise SHaping (MASH) Digital Delta Sigma Modulators (DDSM) comprising first order and second order Error Feedback Modulators is addressed. Exact formulae for cycle lengths with respect to the input, initial conditions, and quantizer modulus are derived for the first and second stages of a MASH 1-2-2 DDSM. In the case of the third stage, the cycle length is found for the special case when it is not divisible by 3 but is divisible by 4. The mathematical analysis is corroborated by MATLAB simulations and by experimental results obtained from a hardware implementation of the MASH 1-2-2 DDSM structure on an FPGA.
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