Abstract
This paper proposes a novel method for Boolean-function minimization which is used for obtaining correct answers in the CAI software for the exercise of logic circuit design. In such CAI application, the number of logic variables is limited to 2 to 5, on the other hand, the running time has to be within a few seconds. At first, the ternary Karnaugh map is proposed. Second, a Boolean-function minimization algorithm using the ternary Karnaugh map is proposed. The minimizing process is as follows: (1) all of the terms obtainable from the given function are generated in the ternary Karnaugh map, (2) redundant terms are sequentially eliminated. The proposed method is compared with the ordinary Quine-McCluskey method. It is found that the maximum processing time can be reduced to one-ninth that using the Quine-McCluskey method.
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