Abstract
Abstract The embedded processor performance is significantly influenced by cache whose performance depend on its architecture parameters. Meanwhile, In order to overcome the non-timing accurate flaw of software simulation method, In this paper, a hardware emulation method --RTL level models is used for CPU and cache controller, while circuit model for cache memory cell--is adopted to do research on cache performance. A more accurate design space, miss rate and cycle trend influenced by cache parameters, is presented. Compared with Round Robin, it shows that miss rate and cycle number of instruction cache is reduced by 22.08% and 20.36%, respectively, because Pseudo- LRU is adopted.
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