Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM

Abstract

Spin-Transfer Torque RAM (STTRAM) is promising for cache applications. However, it brings new data security issues that were absent in volatile memory counterparts such as Static RAM (SRAM). This is primarily due to the fundamental dependency of this memory technology on ambient parameters such as magnetic field and temperature that can be exploited to tamper with the stored data. The magnetic attack could be gradually ramping and/or sudden in nature. In this paper, we propose three techniques to avoid errors in presence of magnetic attack, (a) stalling where the system is halted during attack; (b) cache bypass during gradually ramping attack where the last level cache (LLC) is bypassed and the upper level caches interact directly with the main memory; and, (c) checkpointing along with bypass during sudden attack where the processor states are saved periodically and the LLC is written back at regular intervals. During attack, the system goes back to the last checkpoint and the computation continues with bypassed cache. We performed simulation for different duration and frequency of attack on SPLASH and PARSEC benchmark suites. The results show an average of 13 percent IPC degradation and 6.5 percent energy overhead for a one-time attack lasting for 100 percent of the execution time for cache bypass. For checkpointing to mitigate sudden attack, results show 10 percent IPC degradation and 4.5 percent energy overhead for attack lasting for 50 percent of the execution time.