Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects

Abstract

Inductance effects cannot be neglected in global interconnect lines as well as in circuits operating at higher frequencies. This paper presents a new spatio-temporal bus-encoding technique to minimize simultaneous switching noise as well as reduce delay and power dissipation in on-chip buses where inductance effects are dominating. Simulation experiments are carried out to find out the delay and SSN reduction for interconnect lines of different lengths (2mm, 5mm and 10mm) at various technology nodes (180nm, 130nm, 90nm and 65nm). Results obtained show that that the proposed bus-encoding scheme provides a delay reduction of about 54% to 73% with respect to the worst case delay. In addition, encoding is combined with wire shaping and its impact on further delay reduction is observed to be 4% to 26%. Further, when encoding was combined with wire shaping and repeater insertion, an additional delay reduction of 9% to 33% is observed. Concerning SSN, the encoding scheme is tested with various SPEC'95 benchmarks and it is found that SSN is reduced by about 33% on an average compared with the un-encoded data. Finally, energy minimization of about 13% on an average is achieved by the application of new spatio-temporal encoding scheme as reflected by the SPEC'95 bench mark tests.