Bus in a new light

Abstract

We describe a parallel optical link based on the Siemens' PAROLI DC chip-set-a 22-bit optical parallel bus. A companion link controller has been designed around Xilinx FPGAs, in order to transmit 32-bit data plus 4-bit flags at 40 MHz with parity check. The FPGA design handles the user payload at 40 MHz and performs segmentation and reassembly at 200 MHz. In this work, emphasis is put on the FPGA interface to the Siemens' chip-set-a design which puts to the proof the FPGA architecture. We also present POLAR (Parallel Optical Link Architecture), a VME board which implements a full duplex parallel optical link using this structure: bus in a new light.