Buried-Pt gate InP/In 0.52Al 0.48As/In 0.7Ga 0.3As pseudomorphic HEMTs

Abstract

InP-based high electron mobility transistors (HEMTs) were fabricated by depositing Pt-based multilayer metallization on top of a 6-nm-thick InP etch stop layer and then applying a post-annealing process. The performances of the fabricated 55-nm-gate HEMTs before and after the post-annealing were characterized and were compared to investigate the effect of the penetration of Pt through the very thin InP etch stop layer. After annealing at 250 °C for 5 min, the extrinsic transconductance ( G m ) was increased from 1.05 to 1.17 S/mm and Schottky barrier height was increased from 0.63 to 0.66 eV. The unity current gain cutoff frequency ( f T ) was increased from 351 to 408 GHz, and the maximum oscillation frequency ( f max) was increased from 225 to 260 GHz. These performance improvements can be attributed to penetration of the Pt through the 6-nm thick InP layer, and making contact on the InAlAs layer. The STEM image of the annealed device clearly shows that the Pt atoms contacted the InAlAs layer after penetrating through the InP layer.