Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET

Abstract

The influence of the buried layer structure on the drain-induced barrier lowering (DIBL) is investigated for a silicon-on-insulator metal-oxide-silicon field-effect-transistor (SOI-MOSFET) by a two-dimensional device simulator. The buried layer thickness and the dielectric constant of the buried layer are varied systematically. It is found that the degradation on the threshold voltage can be separated into two components. One component originates from the electric flux via the SOI layer and the other via the buried layer. The buried insulator engineering which controls the thickness and the dielectric constant of the buried layer is effective in reducing the latter component. The gate length limit can be reduced by 23% by the buried air gap structure where the dielectric constant of the buried layer is 1.0.