Abstract
A new high density static RAM cell is designed utilizing a merged junction FET (J-FET) structure. The cell is basically composed of high resistivity-load flipflop and a buried J-FET to supply current to the cell. By eliminating the need for the Al power supply line running through each cell, a smaller-size cell is achieved, i.e. about 900 µm2. To demonstrate the advantages of the new cell, a 2048 word by 8 bit fully static RAM is fabricated with high-performance CMOS (Hi-CMOS) technology. The technology features 3 µm gate length and 4 µm line width. The RAM realizes a typical address access time of 55 ns., and an active power dissipation of 200 mW. The die measures about 26 mm2 and fits into a standard 24 pin package.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
