Buried Interconnects for Sub-5 nm SRAM Design

Abstract

The metal resistance increase due to interconnect pitch scaling was traditionally offset by interconnect length scaling. This is no longer the case for deeply scaled nodes with narrow critical dimensions (CDs) of metals. Static random access memories (SRAMs) route long critical signals such as bitlines and wordlines in lower metal layers of the back-end-of-line (BEOL) and are particularly affected by this metal resistance increase. Buried power rail (BPR) has been proposed in sub-5-nm nodes for routing power and ground lines to improve the performance and density of standard cells and mitigate voltage IR drop issues. We extend the work by exploring the use of buried interconnect for both signal and power routing in SRAMs with minimal process flow changes to the already proposed BPR technology. A high-accuracy 3-D field solver is used for accurate parasitic extraction of SRAM bitcells with buried interconnects. Industry-standard methods are used to evaluate the SRAM macro-level power–performance metrics. We show that the buried interconnects can improve SRAM access time by up to 11%, write time by up to 28%, and dynamic power by 4%, effectively equivalent to one full technology-node gain improvement.