Abstract

Drain to substrate current is an important parameter affecting loss, breakdown and reliability of power GaN HEMTs on Si substrates; however, no clear model of the current has been established. This work proposes a novel approach describing the drain to substrate current as a function of equivalent Si/GaN interface barrier. The modeling results are in close agreement with experimental observations; they reveal an important role of space charge injection from Si substrate into GaN buffer. Compact model closely reproducing experimental data is presented. The results are important for GaN on Si power switches development.

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