Built-In Self-Repair Techniques for Heterogeneous Memory Cores

Abstract

In this paper, BISR (built-in self-repair) techniques for heterogeneous multiple memory cores with divided redundancy mechanism are proposed. Redundant memories are partitioned into row blocks and column blocks and shared among all memory cores in the same memory group. Therefore, unlike the traditional redundancy mechanism, a row (column) block is used as the basic replacement element. Based on the proposed divided redundancy mechanism, a heuristic heterogeneous extended spare pivoting (HESP) redundancy analysis algorithm suitable for built-in implementation is also proposed. Experimental results show that repair rates can be improved significantly due to the efficient usage of redundancy. Moreover, the area overhead of the BISR circuitry for an example with four memory instances is only 1.12%.