Built-in self test of S2I switched current circuits

Abstract

This article presents a new concept for built-in self test of switched current circuits based on S2I memory cells. From the spectrum of possible transistor defects reported in CMOS processes [1] [2], five different fault-situations were modelled and the ability to detect the various failures was studied. This was accomplished by simulating a simple switched-current integrator in which all the different failures were introduced sequentially in all transistors. The fault coverage was derived and the result shows that a powerful system for detection of transistor faults in an analogue sampled-data system can be readily realised with a minimum of additional overhead circuitry.