Abstract
In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared DRAM main memory. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to provide a tight upper bound on the worst-case memory interference in a COTS-based multi-core system. We explicitly model the major resources in the DRAM system, including banks, buses and the memory controller. By considering their timing characteristics, we analyze the worst-case memory interference delay imposed on a task by other tasks running in parallel. To the best of our knowledge, this is the first work bounding the request re-ordering effect of COTS memory controllers. Our work also enables the quantification of the extent by which memory interference can be reduced by partitioning DRAM banks. We evaluate our approach on a commodity multi-core platform running Linux/RK. Experimental results show that our approach provides an upper bound very close to our measured worst-case interference.
Highlights
In multi-core systems, main memory is a major shared resource among processor cores
Our description is based on DDR3 SDRAM systems, but it generally applies to other types of COTS DRAM systems
We assume that all memory requests sent to the DRAM system are misses in the level cache (LLC), which is valid in cache-enabled systems
Summary
In multi-core systems, main memory is a major shared resource among processor cores. Tasks running concurrently on different cores contend with each other to access main memory, thereby increasing their execution times. Previous studies on bounding memory interference delay [9, 43, 32, 37, 5] model main memory as a blackbox system, where each memory request takes a constant service time and memory requests from different cores are serviced in either Round-Robin (RR) or First-Come FirstServe (FCFS) order. This memory model, is not safe for commercial-off-the-shelf (COTS) multi-core systems because it hides critical details necessary to place an upper.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.