Bottom Dielectric Isolation to Suppress Sub-Fin Parasitic Channel of Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Lei Cao,Haoqing Xu,Zhenhua Wu,Yanna Luo,Jiaxin Yao,Qingzhu Zhang,Huaxiang Yin,Yang Liu,Kun Luo,Peng Zhao,Weihai Bu,Yongqin Wu

doi:10.1109/cstic55103.2022.9856910

Bottom Dielectric Isolation to Suppress Sub-Fin Parasitic Channel of Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Lei Cao, Haoqing Xu + Show 10 more

https://doi.org/10.1109/cstic55103.2022.9856910

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Publication Date: Jun 20, 2022

Citations: 2

Affiliation: Institute of Microelectronics, Chinese Academy of Sciences, University of Chinese Academy of Sciences, Semiconductor Manufacturing International (China)

#Nanosheet FETs #Si Nanosheets + Show 8 more

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Abstract

In this paper, to suppress the parasitic channel of sub-fin in vertically stacked gate-all-around (GAA) Si nanosheet FETs (NSFETs), the bottom dielectric isolation (BDI) was designed and simulated using TCAD simulation. The results show that the sub-threshold characteristics of the n-type NSFETs are improved by the BDI approach, and the gate capacitance is reduced by 16.98% compared with that of the NSFETs with sub-fin. In addition, the BDI technology can increase the process and electrical stability of the NSFETs.

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