Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems

Abstract

High performance VLSI systems are being built as multi-processor systems-on-chip. The number of processors and their performance is rising rapidly while the change is slower for the memories. The memory system is often a performance bottleneck in terms of either its bandwidth or latency. We propose sensitivity analysis as a means to pin-point the bottleneck. We introduce a novel randomized technique to measure the sensitivities within cycle accurate simulators. The sensitivity measures identify the bottleneck regions of the design space, within which simplified performance models can be used for optimization. We demonstrate this methodology on the Augmint-MemSim simulator, which is a cycle accurate model for multi-processor systems with a distributed memory sub-system. We empirically show that: (i) Performance predictions from simplified models are strongly correlated with the simulator in the high sensitivity regions. (ii) The simplified models speed up design space exploration by 2 - 3 orders of magnitude over the simulator resulting in better design solutions.